In electromechanical data storage devices such as a disk drive, data being stored is normally recorded onto a magnetic disk in an encoded form consisting of an irregular pattern of ones and zeros. Binary data being recorded is typically synchronous, in that the sequence of ONES and ZEROS making up the data stream occurs with reference to a data bit cell, defined by a uniform or single-frequency clock signal. Recording the clock signal, together with the data, would take up valuable storage room and reduce the data storage capacity of the disk. Using self clocking techniques well known in the art, synchronous binary data is encoded into patterns of ONES and ZEROS, in accord with specific rules regarding the number of consecutive binary ZEROS allowed before a binary ONE signal is required.
Even though some degree of self clocking is inherent in the encoded data, some method of evaluating the encoded data stream must be used in order that a data recovery system may determine how many ZEROS occur consecutively between ONES. In a typical disk drive data recovery system, this function is performed by a data synchronizer which regenerates a synchronous timing reference signal from the encoded data and synchronizes the encoded data stream to that reference. In effect, the data synchronizer generates a synchronous stream of successive windows in time, each window representing a bit cell (in this case, a code bit cell), with which one or more encoded data bit(s) is/are associated. A time period of no ONES may then be referenced to the windows (bit cells) and the number of consecutive ZEROS extracted. For example, six consecutive windows occurring between encoded ONES means there are six consecutive ZEROS in the code. However, the frequency of a recovered synchronization clock synthesized by the data synchronizer is subject to a number of variations introduced by the electronic and mechanical components of the disk drive system. Mechanical system irregularities, such as motor speed variation, spindle bearing noise, actuator flexure, head resonances, and disk platter eccentricity, typically introduce a low-frequency component to the encoded data stream, resulting in a slowly varying read-channel-data rate, while electronic components in the data path typically introduce elements of phase, frequency and write splice noise which are high frequency in nature and more random in their effect on any particular code bit. This last phenomenon is known in the art as "bit jitter". A data synchronizer must take these variations in encoded data frequency into account when synchronizing the data stream.
Common implementations of a data synchronizer include a phase-locked loop (PLL), normally comprising a phase comparator, charge pump, filter, and a means for generating a synchronous feedback (clock) signal, such as a voltage controlled oscillator (VCO). At the beginning of a data read operation, during what is termed velocity lock, the oscillation frequency of the VCO is determined by, and locked to the frequency of, a pulse train recorded in a synchronization field, provided on the data track for such purpose, and occurring just prior in time to the encoded data stream. Once frequency lock is established, the VCO runs in what might be termed a quasi-flywheel mode at a mean frequency determined during velocity lock. Subsequent correction control of the VCO frequency is developed by phase-locking a transition edge of the synchronous VCO signal to a transition edge of an incoming encoded data pulse. The VCO is phase-locked to the incoming encoded data stream by comparing, in the phase comparator, the phase of the rising edge of a data ONE bit to the rising edge of the VCO clock signal. A phase (time) difference between the two rising edges will cause the charge pump to generate a control signal, directing the VCO to either speed up or slow down in response to a frequency variation in the encoded data stream. However, variations due to bit jitter are random in direction as well as frequency. Speeding up the VCO in response to an early-jittered data bit may result in over-correction, especially if the next data bit is jittered late.
A low pass filter is typically provided between the charge pump and the VCO to reject corrections resulting from random high-frequency variations of individual data bits due to bit jitter, and allow ideally only corrections resulting from consistent frequency shifts of the data stream, such as the slowly time-varying perturbations introduced by the mechanical systems discussed earlier. The VCO is therefore locked to the mean phase of the encoded data, rather than to the phase of a particular data bit. Once phase-locked, the synchronous VCO signal provides a recovered clock whose rate (frequency) is equal to the rate at which ONES and ZEROS occur, or an integral multiple thereof. Given perfect frequency and phase-lock of the VCO clock signal to the encoded data stream, the VCO clock might well be used as an analog to the original synchronous clock accompanying the original write data, serving to mark the boundaries of the encoded data bit cells (code bit cells). Perfect phase-lock of VCO to data, however, is not possible due in part to the rejection, within the low pass filter, of VCO phase correction signals resulting from the effects of bit jitter.
The term "bit jitter" refers to the fluctuations in pulse timing which result from a variety of factors, including magnetic surface flatness variations, non-uniformity of the magnetic properties of the media, uncompensated second order peak shift effects, imperfect peak shift precompensation, media deep magnetization, adjacent track pattern interference, incomplete erasure of previous recordings, and magnetic and electrical component noise; displacement of a pulse due to bit jitter being mostly random in both magnitude and direction. The effects of bit jitter on an encoded data stream are illustrated in FIG. 1. Encoded data pulses (FIG. 1b) have been phase-locked to the VCO clock (FIG. 1a), wherein rising edges of the VCO clock and rising edges of the encoded data coincide. Given perfect phase-lock, the rising edges of VCO clock might serve to define synchronous code bit cells (FIG. 1d); a data pulse edge (for instance, a rising edge) occurring within a code bit cell representing a logic ONE, no data edge occurring within a code bit cell representing a logic ZERO. The pulse sequence, illustrated in FIG. 1b, would therefore be read as 010251. Since phase-lock occurs with respect to rising edges 1, an early jittered encoded data pulse rising edge will necessarily occur before the rising edge of the VCO clock signal defining the beginning of the data pulse's respective code bit cell. Referring to FIG. 1c, bit jitter has displaced one pulse (2a) early, one pulse (2b) late, and one pulse (2) not at all. The early jittered pulse 2a falls outside of its respective code bit cell, into the previous cell, causing the data stream pulse sequence to be incorrectly read as 25251 rather than 010251.
The random nature of bit jitter can be appreciated by referring to FIG. 2. Shifts in the nominal position of a data bit due to timing fluctuations (bit jitter) result in a normal distribution of possible transition pulse rising edge positions, distributed, with respect to time, around the occurrence of the VCO clock rising edge 5 with which the nominal phase of the transition pulse rising edge 6 is locked by means of the phase comparator. This phenomenon is described in detail in U.S. Pat. No. 4,809,088, issued on Feb. 28, 1989, and assigned to the same assignee as the present invention. It will be apparent, from inspection of FIG. 2, that, were the VCO clock signal rising edges 5 used to define the code bit cell boundaries 7, there would be approximately a 50% probability that a transition pulse, having rising edge 6, would be jittered early and therefore not captured in the proper code bit cell, giving rise to a read data error. A code bit cell should properly have its boundaries equidistant from, or symmetric about, the mean of a symmetric distribution of transition pulse positions 8, rather than the other way around. Since the triggering edges of the VCO clock signal provide the necessary phase reference to the nominal phase position of a transition pulse in the phase detector, some other means must be provided to capture a transition pulse within a bit cell boundary without regard to its displacement due to jitter.
A data synchronizer must establish what is termed a data detection window or, simply, a "window" around the expected position of a transition pulse. Windows are generated end-to-end in time by the data synchronizer at a repetition rate equal to the VCO clock frequency and, therefore, the channel rate of the data. An ideal window may be looked at as an allotment of time within which a transition edge, if it occurs, will be interpreted as occurring exactly in the window center, thus allowing for random displacement of individual transition pulses due to bit jitter, with no effect on the accuracy of the data recovery error rate. Because of the bell shaped position probability distribution associated with displacements due to bit jitter, it can be seen that for optimum performance, the window must be accurately centered about the mean of this distribution.
The most common prior art data synchronizers employ a phase-locked loop comprising a phase comparator, charge pump, low pass filter and VCO as described previously. The phase comparator receives the data at one input and the VCO output clock on another input for phase comparison. Additionally, the VCO output clock is inverted by an inverter element, and the inverted clock is applied to a data detector as a data detection window. Inversion has the effect of delaying the VCO output clock by one half of its period and thus causing the triggering edges of the inverted clock signal to be substantially symmetric about the position distribution of transition pulses which are then centered within respective data detection windows.
A typical prior art data synchronizer is illustrated in FIG. 3. Connected to receive pulses from a disk drive 3 and pulse detector 3a, it comprises a delay line 10, a data detector 19, a window generator 21, and a phase-locked loop 4 formed of a phase comparator 11, charge pump 17, filter 18, and VCO 14.
As read data is recovered from the disk drive 3, transition pulses 9, representing pulse-formed raw data, are developed in the pulse detector 3a in the drive read channel. The raw data transition pulses are delayed in time by the delay line 10, and the resulting delayed data pulse 12 is directed to an input of the phase comparator 11. The output of the VCO 14 (hereinafter phase detection window clock 13) is applied to the phase comparator 11, where its phase is referenced (compared) to the phase of the input signal (delayed data pulse 12). The phase comparator 11 produced two outputs, pump-up pulse 11a and pump-down pulse 11b. Pump-up pulse 11a is produced if the delayed data pulse 12 leads the phase detection window clock 13, and pump-down pulse 11b is produced if the delayed data pulse 12 lags the phase detection window clock 13. The width of the pulses 11a, 11b reflects the extent of the lead or lag respectively. The outputs 11a, 11b are applied to the charge pump 17, which is operative to apply a source or sink current to the filter 18, depending on whether it receives pulse 11a or 11b. The combination of phase comparator and charge pump is sometimes referred to as a "phase detector" 22 and shall, when appropriate be so referred to herein. In response to the phase detector signal, the filter 18 applies a jitter-free, low-frequency control signal 18a to the VCO 14. The unfiltered control signal's sign depends on whether the delayed data pulse 12 leads or lags, and its magnitude is a function of the extent of the lead or lag. Thus, the output frequency of the VCO 14 is increased or reduced, as appropriate, to reduce the lead or lag at the inputs of the phase comparator 11. The phase-locked loop 4 thus insures that the VCO output, used as the phase detection window clock 13, is locked in phase with the incoming data.
The phase detection window clock 13 is a regular and periodic signal, whereas the occurrence of a data bit is irregular. Attempting to compare the phase of a phase detection window clock 13 to a data ZERO, i.e., when there is no transition pulse edge, would lead to runaway correction, unless the phase comparator 11 was disabled during those times a transition pulse 9 was not present. For this reason, the raw data 9 is directed as a phase error detector enable signal to the enable input 16 of the phase comparator 11. This insures that the phase comparator 11 is enabled just prior to the arrival of a delayed data pulse 12 whose phase is to be compared to that of the phase detection window clock 13.
Data detection occurs in a data detector 19, which functions to determine whether a delayed data pulse 12 occurs within a respective data detection window. The delayed data pulse 12, which is being phase compared to the phase detection window clock 13, is also directed to the input of the data detector 19. The data detector 19 may include a D flip-flop with its D input tied to ground. A data detection window clock 20 is derived from the VCO's phase detection window clock 13 by inverting that signal through an inverting means 21 provided in the window generator 21. Inversion of the phase detection window clock 13 seeks to construct a data detection window clock 20 having the same period as the phase detection window clock 13, and having a 180.degree. phase relationship therewith, such that successive triggering edges of the data detection window clock 20 bracket successive triggering edges of the phase detection window clock 13. Since triggering edges of the phase detection window clock 13 are phase-locked with the delayed data pulses 12, the triggering edges of the data detection window clock 20 will therefore bracket the delayed data pulses 12 as well. The object of this data detection window clock 20 is to provide a synchronous stream of time windows, within which the distribution of positions of delayed data pulses 12 (when they occur) is centered, such that bit jitter merely displaces a pulse within the window. If a delayed data pulse 12 occurs within a particular data detection window, the data detection window clock 20 provides the additional function of clocking the D flip-flop within the data detector 19 such that a data pulse, so detected, is synchronously latched into the D flip-flop by action of the data detection window clock 20 and is available on the output of the data detector 19 as a stable, synchronized data signal, having a fixed relationship with the data detection window clock 20, and having the position variations due to bit jitter removed.
The main shortcoming of prior art data synchronizers relying on inverter elements to derive a data detection window clock 20 from the phase detection window clock 13 is that the inherent internal delay of an inverter element precludes the data detection window clock 20 from being exactly 180.degree. out-of-phase with the phase detection window clock 13, and therefore from exactly symmetrically bracketing the distribution of delayed data pulses 12. Power supply voltage fluctuations, temperature variations and manufacturing parameter drift combine to distort the symmetry of an inverter's output characteristic, making it a less-than-ideal phase shifter. This lack of symmetry has significant implications for high-speed, low-error-rate data recovery systems.
Error rate is defined as the number of data bits read before a detection error is encountered. For example, a 10.sup.-10 error rate means that one detection error will occur, on average, for every 10.sup. data bits recovered from the disk drive. In practice, lack of perfect symmetry between the data detection window clock 20 and the phase detection window clock 13 selectively shifts the boundaries of the detection window relative to the center of the data pulse position distribution. Any offset from center, in the detection window boundaries, will allow a portion of a tail of the data pulse position distribution to fall outside the detection window, in the direction away from the window offset, increasing the error rate, i.e., a detection window which is offset late by inherent delay, will not detect a data pulse positioned very early in the distribution. Error rate increases to the extent data pulses drift beyond the window boundaries.
Given an acceptable error rate for a particular window width, such as 10.sup.-10, for a 40-nanosecond window width, a suitable means for determining whether that rate has been exceeded becomes desirable. A known technique for ascertaining error rate is to shift the window relative to the delayed data pulses 12, which has the effect of narrowing the window, causing a data pulse to fall outside it after a fewer number of total delayed pulses than without window shift. Since the error rate curve, when plotted on a logarithmic scale, is nearly linear along a substantial portion of its opposite legs (see FIG. 5 of the above-referenced patent), measurements with a few progressively-greater window shifts can be used to extrapolate error rates for relatively tighter windows. Thus, for example, a measurement might be taken with a window shift which will cause one pulse to fall outside the window after the occurrence of 10.sup.7 pulses, and another reading with a window shift which will cause one pulse to fall outside after the occurrence of 10.sup.5 pulses. The detected error rate resulting from such window shifts could then be extrapolated to predict the window width that would result in one pulse out of 10.sup.10 falling outside the window or, conversely, the number of pulses that would be required before one pulse falls outside the window whose width is 40 nanoseconds.
Expensive test equipment is available to bring about window shifting externally of the disk drive. A preferred alternative is to provide equipment which is built into the disk drive equipment and which enables window shifting without use of external equipment. One such alternative system is disclosed in the above-referenced patent. In pertinent part, it includes a data synchronizer having a disk drive, phase-locked loop, and data detector similar to those illustrated in FIG. 3. In the system disclosed in the referenced patent, a variable delay is interposed in the path between the disk drive and the data detector whereby the delayed pulse from the disk drive is further delayed by a variable amount relative to the window clock.
Among the objects of the invention disclosed in an application filed Apr. 12, 1991 by Wilson et al., U.S. patent application Ser. No. 07/685473, the present assignee and incorporated herein by this reference, is to provide a disk drive data synchronizer in which the distribution of possible bit-jittered positions of a data pulse is precisely centered within a data detection window.
These and other objects are attained in accordance with the referenced invention by a disk drive data synchronizer which derives from an irregular series of data pulses in a pulse train (such as delayed data pulses 12) window clock signals designating successive time periods (T), each window clock signal being dedicated to the discerning of the presence or absence of a respective one of the data pulses during a respective one of the time periods and to the synchronization of a discerned one of those data pulses. The synchronizer comprises four principal elements: variable frequency means, a symmetric window generator, phase detector means, and data detector means. The variable frequency means generates a first periodic (VCO) clock signal whose nominal frequency is an integral multiple of the frequency of the pulse train and whose frequency is variable in response to a frequency control signal. The symmetric window generator is driven by the first clock signal and generates second and third periodic clock signals (phase detection window clock and data detection window clock) in response to, and at an integral submultiple of the frequency of, the first clock signal. The second and third clock signals are phased exactly 180 .degree. apart. The phase detector means produces a phase detector signal representative of the sign and magnitude of the phase difference between the second clock signal and the data pulses. Provided with the phase detector means are means for applying the average of the phase detector signal to the variable frequency means as its frequency control signal. Finally, the data detector means is responsive to the third clock signal and to the data pulses for discerning the presence or absence of a data pulse during each of the time periods (T) and synchronizing the discerned data pulse with respect to the third clock signal.
In further keeping with the referenced invention, the window generator comprises an integrated circuit having a line of symmetry separating substantially identical halves of the integrated circuit, each half having an output on which is carried a respective one of the second and third clock signals. More specifically, each half of the window generator comprises a respective one of a pair of cross-connected logic gates and a feedback loop connected between the output of the cross-connected logic gates and its input. In accordance with this aspect of the referenced invention, the integrated circuit is a frequency divider having first and second mutually exclusive states, and each feedback loop includes means for conditionally enabling it during portions of the times during which respective ones of those states prevail.